1. Field of the Disclosure
The disclosure relates to integrated circuit chips and chip packages, and more particularly, to integrated circuit chips and packages that utilize differing interconnection schemes for different sides of the circuit chips and packages.
2. Brief Description of the Related Art
Semiconductor chips can be found in many electronic devices, and today many electronic devices are required to run at high speed and/or low power consumption conditions. In traditional semiconductor fabrication, a chip can use wirebonding wires or solder balls bonded with pads, exposed by openings in a passivation layer of the chip, of the chip to connect with a ball grid array (BGA) substrate. Modern electronic systems, modules, and/or circuit boards typically contain many different types of chips, such central processing units (CPUs), digital signal processors (DSPs), analog chips, dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, flash memory chips, and the like.
Each chip is typically fabricated using different types and/or different generations of IC manufacturing process technologies. For example, in some notebook personal computers, a CPU chip might be fabricated using a 65 nm IC process technology with a power supply voltage of 1.2V, an analog chip might be fabricated using an older 0.25 micron (250 nm) IC process technology with a power supply voltage of 3.3V, and a DRAM chip might be fabricated using a 90 nm IC process technology at 1.5V, and a flash memory chip might be fabricated using a 0.18 micron (180 nm) IC process technology with power supply voltage at 2.5V.
Each different type of chip can require a different voltage requirement for its supplied power. For example, a given DRAM chip might require an on-chip voltage converter to convert 3.3V to 1.5V while a flash memory chip might at the same time require an on-chip voltage converter to convert 3.3V to 2.5V. With a variety of supply voltages in a single system, voltage regulation and conversion can be problematic, complicated, and costly.
Interconnection schemes include the metal connections that connect an IC to other circuit or system components. Such interconnection schemes have become of relative importance and have, with the further miniaturization of the IC, an increasingly negative impact on the circuit performance, including for chip voltage and regulation. For example, the parasitic capacitance and resistance of the metal interconnections increase with smaller scale, which degrades the chip performance significantly. Of significant concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.
To solve this problem, one approach has been to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines. Current practice is to create metal interconnection networks under a layer of passivation, this approach however limits the interconnect network to fine line interconnects and the therewith associated high parasitic capacitance and high line resistivity. The latter two parameters, because of their relatively high values, degrade device performance, an effect which becomes even more severe for higher frequency applications and for long interconnect lines that are, for instance, used for clock distribution lines. Also, fine line interconnect metal cannot carry high values of current that is typically needed for ground busses and for power busses.